A self-checking generalized prediction checker and its use for built-in testing
IEEE Transactions on Computers
Strongly Fault Secure PLAs and Totally Self-Checking Checkers
IEEE Transactions on Computers
Fault-tolerant computer system design
Fault-tolerant computer system design
Embedded Totally Self-Checking Checkers: A Practical Design
IEEE Design & Test
Self-Checking Comparator with One Periodic Output
IEEE Transactions on Computers
Embedded two-rail checkers with on-line testing ability
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
Low Cost and High Speed Embedded Two-Rail Code Checker
IEEE Transactions on Computers
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This paper presents a new simple and straightforward method for designing Completely Testable Embedded (CTE) parity trees, and Self-Testing Embedded (STE) two-rail checkers. In the design of CTE parity trees the two inputs XOR gate has been used as the building block. In the case of STE two-rail checkers with n input pairs the building block is thetwo-rail checker with 2 input pairs. During normal, fault free, operationeach XOR gate receives all possible input vectors, while each two-railchecker with 2 input pairs receives all possible code input vectors. Thegreat advantage of the proposed method is that it is the only one thatgives in a simple and straightforward way an optimal CTE/STE treerealization with respect to the hardware (number of blocks) and the speed(number of block levels). Designing the two input two-rail checker asproposed by Lo in IEEE J. of Solid-State Circuits,1993, we get optimal STE two-rail checkers taking into account realisticfaults.