A note on strongly fault-secure sequential circuits
IEEE Transactions on Computers
Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes
IEEE Transactions on Computers
Design of Self-Testing Checkers for Borden Codes
IEEE Transactions on Computers
Design of self-testing checkers for m-out-of-n codes using parallel counters
On-line testing for VLSI
Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
Concurrent Error Detection Using Monitoring Machines
IEEE Design & Test
Design of TSC Code-Disjoint Inverter-Free PLA's for Separable Unordered Codes
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers
Unified Design of Self-Checking and Fail-Safe Combinational Circuits and Sequential Machines
IEEE Transactions on Computers
State encoding and minimization methodology for self-checking sequential machines
EUROCAST'11 Proceedings of the 13th international conference on Computer Aided Systems Theory - Volume Part I
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Several design methods of self-checking synchronous sequential circuits (SMs) have been proposed in the literature. In this paper, we present a new approach to designing totally self-checking (TSC) code-disjoint (CD) SMs protected against errors using unordered codes. It is assumed that D flip-flops are used as the memory elements and that the circuit should be TSC for all single stuck-at faults (except for the faults on the clock lines), and CD for all input unidirectional errors. The initial 2-level AND-OR equations (with all products shared) are checked for self-testing by verifying some algebraic conditions. All stuck-at-1 faults which cannot be detected during normal functioning are identified. Then, the circuit is modified to the AND-AND-OR circuit with generally higher fault coverage. The resulting circuit is minimized using the well known SIS CAD tools. The whole design process has been automated by using the newely developed software tools that accept the BLIF representation of a SM and are compatible with the SIS tools. Many benchmark SMs can now be implemented as TSC with 100% fault coverage.