Logic-Level Analysis of Fault Attacks and a Cost-Effective Countermeasure Design

  • Authors:
  • Masahiro Kaminaga;Takashi Watanabe;Takashi Endo;Toshio Okochi

  • Affiliations:
  • -;-;-;-

  • Venue:
  • IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  • Year:
  • 2008

Quantified Score

Hi-index 0.00

Visualization

Abstract

This article analyzes the internal mechanism of fault attacks on microcontrollers and proposes a cost-effective hardware and software countermeasure design policy. Reliable branch operations are essential to DFA-resistant hardware. Our method is based on a logical fault attack simulation to find the minimum set of signals that contribute to faults in the branch operations and is also based on applying partially redundant logic.