An Investigation into the Security of Self-Timed Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A behavioral synthesis system for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and Analysis of Dual-Rail Circuits for Security Applications
IEEE Transactions on Computers
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Logic-Level Analysis of Fault Attacks and a Cost-Effective Countermeasure Design
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Application of Concurrency in the Asynchronous Design of Write-after-read Operations
Fundamenta Informaticae - Application of Concurrency to System Design
Asynchronous data-driven circuit synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Path swapping method to improve DPA resistance of quasi delay insensitive asynchronous circuits
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Application of Concurrency in the Asynchronous Design of Write-after-read Operations
Fundamenta Informaticae - Application of Concurrency to System Design
Design of a low-power embedded processor architecture using asynchronous function units
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
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SPA is a synthesised, self-timed, ARM-compatible processor core. The use of synthesis was mandated by a need for rapid implementation. This has proved to be very effective, albeit with increased cost in terms of area and performance compared with earlier non-synthesised processors. SPA is employed in an experimental smartcard chip which is being designed to evaluate the applicability of self-timed logic in security-sensitive devices. The Balsa synthesis system is used to generate dual-rail logic with some enhancements to improve security against non-invasive attacks. A complete system-on-chip is being synthesised with a only small amount of hand design being employed to boost the throughput of the on-chip interconnection system.