Efficient self-timing with level-encoded 2-phase dual-rail (LEDR)
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
IEEE Transactions on Computers
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Delay-Insensitive Pipelined Communication on Parallel Buses
IEEE Transactions on Computers
Asynchronous Comparison-Based Decoders for Delay-Insensitive Codes
IEEE Transactions on Computers
Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
Towards Totally Self-Checking Delay-Insensitive Systems
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Efficient Systematic Error-Correcting Codes for Semi-Delay-Insensitive Data Transmission
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Leakage-and crosstalk-aware bus encoding for total power reduction
Proceedings of the 41st annual Design Automation Conference
Error-correction and crosstalk avoidance in DSM busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers
Theory of Unidirectional Error Correcting/Detecting Codes
IEEE Transactions on Computers
A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
Asynchronous transient resilient links for NoC
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A new delay-insensitive data encoding scheme for global asynchronous communication is introduced. The goal of this work is to combine the timing-robustness of delay-insensitive (i.e., unordered) codes with the fault-tolerance of error-correcting codes. The proposed error-correcting unordered (ECU) code, called Zero-Sum, can safely accommodate arbitrary skew in arrival times of individual bits in a packet, while simultaneously providing 1-bit correction and 2-bit detection. A systematic code is targeted, where data can be directly extracted from the codewords. A basic method for generating the code is presented, as well as detailed designs for the supporting hardware blocks. An outline of the system micro-architecture and its operating protocol is also given. When compared to the best previous systematic ECU code, the new code provides a 5.74 to 18.18% reduction in transition power for most field sizes, with better or comparable coding efficiency. Pre-layout technology-mapped implementations of the supporting hardware (encoder, completion detector, error-corrector) were synthesized with the UC Berkeley ABC tool using a 90nm industrial standard cell library. Results indicate that they have moderate area and delay overheads, while the best non-systematic ECU codes have 3.82 to 10.44x greater area for larger field sizes.