The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
IEEE Transactions on Computers
Asynchronous Circuits for Low Power: A DCC Error Corrector
IEEE Design & Test
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
IEEE Design & Test
Codes for Detecting and Correcting Unidirectional Errors
Codes for Detecting and Correcting Unidirectional Errors
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Delay-Insensitive Pipelined Communication on Parallel Buses
IEEE Transactions on Computers
Membership Test Logic for Delay-Insensitive Codes
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Limitations of VLSI implementation of delay-insensitive codes
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
An error-correcting unordered code and hardware support for robust asynchronous global communication
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 14.98 |
A comparison-based decoder detects the arrival of a code word by comparing the received checkbits with the checkbits computed using the received data. Implementation issues underlying comparison-based decoders for systematic delay-insensitive (DI) or unordered codes is the subject of this paper. We show that if the decoder is to be implemented using asynchronous logic, i.e., if the gate and wire delays are arbitrary (unbounded but finite), then it is impossible to design a comparison-based decoder for any code that is more efficient than a dual-rail code. In other words, the encoded word must contain at least twice as many bits as the data. In addition, the codes should satisfy two other properties, called the initial condition and the all-zero lower triangle (AZLT) property, for the realization of a delay-insensitive comparison-based decoder. The paper shows that comparison-based decoders for codes that have the requisite level of redundancy and that satisfy the two properties can be implemented using asynchronous logic.