An investigation of power delay trade-offs on PowerPC circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Bus encoding for low-power high-performance memory systems
Proceedings of the 37th Annual Design Automation Conference
Future performance challenges in nanometer design
Proceedings of the 38th annual Design Automation Conference
Simultaneous shield insertion and net ordering under explicit RLC noise constraint
Proceedings of the 38th annual Design Automation Conference
Coupling-driven bus design for low-power application-specific systems
Proceedings of the 38th annual Design Automation Conference
Low-leakage asymmetric-cell SRAM
Proceedings of the 2002 international symposium on Low power electronics and design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Design Challenges of Technology Scaling
IEEE Micro
The scaling challenge: can correct-by-construction design help?
Proceedings of the 2003 international symposium on Physical design
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Adapative Error Protection for Energy Efficiency
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Design and CAD Challenges in sub-90nm CMOS Technologies
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Leakage-Aware Interconnect for On-Chip Network
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Proceedings of the conference on Design, automation and test in Europe
Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnects
International Journal of High Performance Systems Architecture
An error-correcting unordered code and hardware support for robust asynchronous global communication
Proceedings of the Conference on Design, Automation and Test in Europe
Designing efficient codecs for bus-invert berger code for fully asymmetric communication
IEEE Transactions on Circuits and Systems II: Express Briefs
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Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates capacitive crosstalk while simultaneously reducing total power. We introduce a new buffer design approach with selective use of high threshold voltage transistors and couple this buffer design with a novel bus encoding scheme. The proposed encoding scheme significantly reduces total power by 26% and runtime leakage power by 42% while also eliminating capacitive crosstalk. In addition, the proposed encoding is specifically optimized to reduce the complexity of the encoding logic, allowing for a significant reduction in overhead which has not been considered in previous bus encoding work.