Leakage-Aware Interconnect for On-Chip Network

Authors:
Yuh-Fang Tsai;Vijaykrishnan Narayaynan;Yuan Xie;Mary Jane Irwin
Affiliations:
Penn State University;Penn State University;Penn State University;Penn State University
Venue:
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Year:
2005

Citing 2
Cited 1

Leakage power modeling and optimization in interconnection networks

Proceedings of the 2003 international symposium on Low power electronics and design
Leakage-and crosstalk-aware bus encoding for total power reduction

Proceedings of the 41st annual Design Automation Conference

On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect

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Abstract

On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes. Our schemes achieve 10.13%~63.57% active leakage savings and 12.35%~95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.