An investigation of power delay trade-offs on PowerPC circuits

  • Authors:
  • Qi Wang;Sarma B. K. Vrudhula;Shantanu Ganguly

  • Affiliations:
  • Center for Low Power Electronics, ECE Dept., University of Arizona Tucson, AZ;Center for Low Power Electronics, ECE Dept., University of Arizona Tucson, AZ;Somerset Design Center, Motorola Inc., Austin, TX

  • Venue:
  • DAC '97 Proceedings of the 34th annual Design Automation Conference
  • Year:
  • 1997

Quantified Score

Hi-index 0.00

Visualization

Abstract

Logic and structural transformations to reduce power havebeen considered by a number of authors.However,all the results presented so far have been based on modelsof power and estimation methods that may not be a accuratereflection of 'real world' constraitns.The performancerequirements of industrial designs often significantly restrictthe applicability of the power reducing transformations.Inthis paper we present the results of investigations on the efficacyof a recently reported logic level power optimizing algorithmon some commercial circuits, using customer suppliedinput waveforms.Based on a accurate delay model,the power consumption of the circuits is estimated using thecommercial package called 'PowerMill".The experimental resultsshow that a maximum 21% average power and 27.7%peak power power reduction can be obtained with only 3% delayincrease.Based on the experiments, we propose a generalmethodology for the practical application of the transformationsfor power optimization of CMOS logic circuits.Finally,a comparison between the experiments using randominput waveforms and customer provided input waveforms ispresented.