Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level power optimization of special purpose applications: the beach solution
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Coding a terminated bus for low power
GLSVLSI '95 Proceedings of the Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
Some Issues in Gray Code Addressing
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Energy exploration and reduction of SDRAM memory systems
Proceedings of the 39th annual Design Automation Conference
Low-energy off-chip SDRAM memory systems for embedded applications
ACM Transactions on Embedded Computing Systems (TECS)
Energy-Monitoring Tool for Low-Power Embedded Programs
IEEE Design & Test
Weight-Based Bus-Invert Coding for Low-Power Applications
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Memory Bus Encoding for Low Power: A Tutorial
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Leakage-and crosstalk-aware bus encoding for total power reduction
Proceedings of the 41st annual Design Automation Conference
Frequent value encoding for low power data buses
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Web-Based Energy Exploration Tool for Embedded Systems
IEEE Design & Test
BEAM: bus encoding based on instruction-set-aware memories
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Bus encoding for total power reduction using a leakage-aware buffer configuration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Invited talk: in-house tools for low-power embedded systems
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
CACTI-IO: CACTI with off-chip power-area-timing models
Proceedings of the International Conference on Computer-Aided Design
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High-performance memory buses consume large energy as they include termination networks, BiCMOS and/or open-drain output. This paper introduces power reduction techniques for memory systems deliberating on burst-mode transfers over the high-speed bus specifications such as Low Voltage BiCMOS (LVT), Gunning Transfer Logic (GTL+) and Stub Series Termination Logic (SSTL_2) which are widely used. The reduction techniques take both the static and the dynamic power consumption into account because most high-performance bus drivers and end-termination networks dissipate significant static power as well. Extensive performance analysis is conducted through mathematical analysis and trace data-driven simulations. We had reduction of 14% with random data and up to 67.5% with trace data.