Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cache design trade-offs for power and performance optimization: a case study
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Survey of low power techniques for ROMs
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
System-level power optimization of special purpose applications: the beach solution
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Analytical energy dissipation models for low-power caches
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Analysis of power consumption in memory hierarchies
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Memory modeling for system synthesis
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Synthesis of low-overhead interfaces for power-efficient communication over wide buses
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Memory exploration for low power, embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Cycle-accurate simulation of energy consumption in embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Conforming inverted data store for low power memory
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
Bus encoding for low-power high-performance memory systems
Proceedings of the 37th Annual Design Automation Conference
Quantifying the energy consumption of a pocket computer and a Java virtual machine
Proceedings of the 2000 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMI
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Power-optimal encoding for DRAM address bus (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
PASTEL: a parameterized memory characterization system
Proceedings of the conference on Design, automation and test in Europe
Address bus encoding techniques for system-level power optimization
Proceedings of the conference on Design, automation and test in Europe
Memory controller policies for DRAM power management
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
ATS '98 Proceedings of the 7th Asian Test Symposium
PowerScope: A Tool for Profiling the Energy Usage of Mobile Applications
WMCSA '99 Proceedings of the Second IEEE Workshop on Mobile Computer Systems and Applications
Software Power Estimation and Optimization for High Performance, 32-bit Embedded Processors
ICCD '98 Proceedings of the International Conference on Computer Design
Architectural-level power estimation for system-on-a-chip
Architectural-level power estimation for system-on-a-chip
Policy optimization for dynamic power management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Memory-aware energy-optimal frequency assignment for dynamic supply voltage scaling
Proceedings of the 2004 international symposium on Low power electronics and design
A compressed frame buffer to reduce display power consumption in mobile systems
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
DLS: dynamic backlight luminance scaling of liquid crystal display
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Web-Based Energy Exploration Tool for Embedded Systems
IEEE Design & Test
Energy-aware data compression for multi-level cell (MLC) flash memory
Proceedings of the 44th annual Design Automation Conference
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
In-order pulsed charge recycling in off-chip data buses
Proceedings of the 18th ACM Great Lakes symposium on VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-level power estimation using an on-chip bus performance monitoring unit
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
An approach for adaptive DRAM temperature and power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-Efficient microkernel of embedded operating system on chip
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Invited talk: in-house tools for low-power embedded systems
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
Functional-Level Energy Characterization of µC/OS-II and Cache Locking for Energy Saving
Bell Labs Technical Journal
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Memory systems are dominant energy consumers, and thus many energy reduction techniques for memory buses and devices have been proposed. For practical energy reduction practices, we have to take into account the interaction between a processor and cache memories together with application programs. Furthermore, energy characterization of memory systems must be accurate enough to justify various techniques. In this article, we build an in-house energy simulator for memory systems that is accelerated by special hardware support while maintaining accuracy. We explore energy behavior of memory systems for various values of the processor and memory clock frequencies and cache configuration. Each experiment is performed with 24M instruction steps of real application programs to guarantee accuracy.The simulator is based on precise energy characterization of memory systems including buses, bus drivers, and memory devices by a cycle-accurate energy measurement technique. We characterize energy consumption of each component by an energy state machine whose states and transitions are associated with the dynamic and static energy costs, respectively. Our approach easily characterizes the energy consumption of complex SDRAMs. We divide and quantify energy components of main memory systems for high-level reduction. The energy simulator enables us to devise practical energy reduction schemes by providing the actual amount of reduction out of the total energy consumption in main memory systems. We introduce several practical energy reduction techniques for SDRAM memory systems and demonstrate energy reduction ratio over the SDRAM memory systems with commercial SDRAM controller chipsets. We classify the SDRAM memory systems into high-performance and mid-performance classes and achieve suitable system configurations for each class. For instance, a typical high-performance 32-bit, 64 MB SDRAM memory system consumes 19.6 mJ, 33.8 mJ, 35.4 mJ, and 37.0 mJ for 24M instructions of an MP3 decoder, a JPEG compressor, a JPEG decompressor, and an MPEG4 decoder, respectively. Our reduction scheme saves 12.7 mJ, 15.1 mJ, 15.5 mJ, and 14.8 mJ, and the reduction ratios are 64.8%, 44.6%, 43.8%, and 40.1%, respectively, without compromising execution speed.