Voltage scheduling problem for dynamically variable voltage processors
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Nonideal battery and main memory effects on CPU speed-setting for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Dynamic voltage scaling and power management for portable systems
Proceedings of the 38th annual Design Automation Conference
Energy exploration and reduction of SDRAM memory systems
Proceedings of the 39th annual Design Automation Conference
Low-energy off-chip SDRAM memory systems for embedded applications
ACM Transactions on Embedded Computing Systems (TECS)
Processor Voltage Scheduling for Real-Time Tasks with Non-Preemptible Sections
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
The synergy between power-aware memory systems and processor voltage scaling
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
High-level power management of embedded systems with application-specific energy cost functions
Proceedings of the 43rd annual Design Automation Conference
Cross-component energy management: Joint adaptation of processor and memory
ACM Transactions on Architecture and Code Optimization (TACO)
PVS: passive voltage scaling for wireless sensor networks
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Energy-efficient dynamic task scheduling algorithms for DVS systems
ACM Transactions on Embedded Computing Systems (TECS)
System-wide energy minimization for real-time tasks: Lower bound and approximation
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the Conference on Design, Automation and Test in Europe
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Dynamic supply voltage scaling (DVS) is one of the best ways to reduce the energy consumption of a device when there is a super-linear relationship between energy and supply voltage, and a pseudo-linear relationship between delay and supply voltage. However, most DVS schemes scale the clock frequency of the supply-voltage-clock-scalable (SVCS) CPU only and do not address the energy consumption of the memory. The memory is generally non-supply-voltage-scalable (NSVS), but its energy consumption is variable to its clock frequency and the total execution time. Thus, DVS for an SVCS CPU cannot achieve an optimal system-wide energy saving without consideration of the memory, as far as it is controlled by an SVCS CPU.We introduce an energy-optimal frequency assignment, for both an SVCS CPU and a synchronous NSVS memory, which optimizes the system-wide energy consumption. We derive the energy-optimal clock frequencies for an SVCS CPU and a synchronous NSVS memory, as a function of the number of processor clock cycles, the number of memory accesses and the hardware energy model. Our technique modifies the frequency assignment of the CPU and the memory used in previous DVS schemes, which ignore the memory energy. It enables the system-wide energy-optimal settings and achieves additional 50% energy reduction over previous DVS schemes. This technique can also be applicable to synchronous NSVS peripheral devices.