MIPS RISC architectures
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level power optimization of special purpose applications: the beach solution
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Computer architecture (2nd ed.): a quantitative approach
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Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
Reducing Address Bus Transitions for Low Power Memory Mapping
EDTC '96 Proceedings of the 1996 European conference on Design and Test
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Some Issues in Gray Code Addressing
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
System-level power optimization of special purpose applications: the beach solution
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Power estimation for architectural exploration of HW/SW communication on system-level buses
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Influence of caching and encoding on power dissipation of system-level buses for embedded systems
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Synthesis of low-overhead interfaces for power-efficient communication over wide buses
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Power optimization of system-level address buses based on software profiling
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power-optimal encoding for DRAM address bus (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Power optimization and management in embedded systems
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Low power techniques for address encoding and memory allocation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-energy for deep-submicron address buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Irredundant address bus encoding for low power
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Power-optimal encoding for a DRAM address bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-energy off-chip SDRAM memory systems for embedded applications
ACM Transactions on Embedded Computing Systems (TECS)
Power: A First Class Design Constraint for Future Architecture and Automation
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Weight-Based Bus-Invert Coding for Low-Power Applications
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Low Power-Delay Product Page-Based Address Bus Coding Method
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Memory Bus Encoding for Low Power: A Tutorial
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Tiny instruction caches for low power embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
An evolutionary approach for reducing the energy in address buses
ISICT '03 Proceedings of the 1st international symposium on Information and communication technologies
Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work
Proceedings of the conference on Design, automation and test in Europe - Volume 1
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
Power-Efficient Wakeup Tag Broadcast
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Irredundant address bus encoding techniques based on adaptive codebooks for low power
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint
Proceedings of the 43rd annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
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Energy optimization of multiprocessor systems on chip by voltage selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simultaneous on-chip bus synthesis and voltage scaling under random on-chip data traffic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing-aware power-optimal ordering of signals
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems
Transactions on High-Performance Embedded Architectures and Compilers I
NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnects
International Journal of High Performance Systems Architecture
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Power aware external bus arbitration for system-on-a-chip embedded systems
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
Bus power estimation and power-efficient bus arbitration for system-on-a-chip embedded systems
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
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The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I/O interfaces can provide significant savings on the overall power budget. This paper presents innovative encoding techniques suitable for minimizing the switching activity of system-level address buses. In particular, the schemes illustrated here target the reduction of the average number of bus line transitions per clock cycle. Experimental results, conducted on address streams generated by a real microprocessor, have demonstrated the effectiveness of the proposed methods.