Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting the locality of memory references to reduce the address bus energy
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Partial bus-invert coding for power optimization of system level bus
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Power optimization of core-based systems by address bus encoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power optimization of system-level address buses based on software profiling
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Address bus encoding techniques for system-level power optimization
Proceedings of the conference on Design, automation and test in Europe
Irredundant address bus encoding for low power
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Extension of the Working-Zone-Encoding Method to Reduce the Energy on the Microprocessor Data Bus
ICCD '98 Proceedings of the International Conference on Computer Design
A Low-Energy Adaptive Bus Coding Scheme
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
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The working-zone encoding (WZE) method employinglocality of memory reference was previously proposed toreduce address bus switching activity. This paper presentsan encoding method that retains the advantage of WZE inswitching activity reduction, but does not incur excessivepath delay and area overhead. The proposed method isscalable for large bus width. Our encoder (decoder) hasup to 58% (64%) delay reduction and 70% (62%) areareduction for a 32-bit multiplexed address bus. Theswitching activity is increased by 15% (18%) for the casewithout (with) a cache if the switching activity overheadis not counted. If the overhead is counted, the switchingactivity is reduced by 32% (17%) for the case without(with) a cache.