Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level power optimization of special purpose applications: the beach solution
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Partial bus-invert coding for power optimization of system level bus
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Synthesis of low-overhead interfaces for power-efficient communication over wide buses
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Address bus encoding techniques for system-level power optimization
Proceedings of the conference on Design, automation and test in Europe
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Bus-switch coding for reducing power dissipation in off-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we describe a new encoding technique which reduces bus line transition activity for power-efficient data transfer over wide system buses. The focus is on data streams whose statistical parameters such as transition activity are either non-stationary or a priori unknown. The proposed encoding technique extends the Partial Businvert encoding method [1] with a dynamic selection of the bus lines to be encoded. In this work, we present the encoding algorithm and a low power implementation of a corresponding coder-decoder system. Experiments with real-life data streams yielded a reduction in transition activity of up to 42 % compared to the uncoded data stream.