System level power estimation of system-on-chip interconnects in consideration of transition activity and crosstalk

Authors:
Martin Gag;Tim Wegner;Dirk Timmermann
Affiliations:
Institute of Applied Microelectronics and Computer Engineering, University of Rostock;Institute of Applied Microelectronics and Computer Engineering, University of Rostock;Institute of Applied Microelectronics and Computer Engineering, University of Rostock
Venue:
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Year:
2010

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Abstract

As technology reaches nanoscale order, interconnection systems account for the largest part of power consumption in Systemson-Chip. Hence, an early and sufficiently accurate power estimation technique is needed for making the right design decisions. In this paper we present a method for system-level power estimation of interconnection fabrics in Systems-on-Chip. Estimations with simple average assumptions regarding the data stream are compared against estimations considering bit level statistics in order to include low level effects like activity factors and crosstalk capacitances. By examining different data patterns and traces of a video decoding system as a realistic example, we found that the data dependent effects are not negligible influences on power consumption in the interconnection system of nanoscale chips. Due to the use of statistical data there is no degradation of simulation speed in our approach.