ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Low-power encodings for global communication in CMOS VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Low-swing interconnect interface circuits
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-energy for deep-submicron address buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combining wire swapping and spacing for low-power deep-submicron buses
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Optimum positioning of interleaved repeaters In bidirectional buses
Proceedings of the 40th annual Design Automation Conference
Energy-reliability trade-off for NoCs
Networks on chip
A dictionary-based en/decoding scheme for low-power data buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Power analysis of system-level on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime
Proceedings of the 2006 international workshop on System-level interconnect prediction
BEAM: bus encoding based on instruction-set-aware memories
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Multi-parametric improvements for embedded systems using code-placement and address bus coding
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Reducing the Data Switching Activity on Serial Link Buses
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Serial-link bus: a low-power on-chip bus architecture
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Exploiting on-chip data behavior for delay minimization
Proceedings of the 2007 international workshop on System level interconnect prediction
Adaptive data compression for high-performance low-power on-chip networks
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Delay-efficient bus encoding techniques
Microprocessors & Microsystems
Serial-link bus: a low-power on-chip bus architecture
IEEE Transactions on Circuits and Systems Part I: Regular Papers
NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnects
International Journal of High Performance Systems Architecture
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus-switch coding for reducing power dissipation in off-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The energy dissipation associated with driving long wires accounts for a significant fraction of the overall system energy. This is particularly the case with the increasing importance of the inter-wire parasitic capacitance in deep sub-micron technology. A closed form solution for estimating the energy dissipation of a data bus is presented that uses an elaborate parasitic wire model. This includes the distributed RLC effects of wires as well as the coupling between wires. We also propose a general class of coding techniques to reduce energy dissipation for data transmission by trading-off between computation and communication costs. An algorithm is presented to design efficient coding strategies to minimize energy. When the effects of inter-wire capacitance are taken into account, the best coding strategy is not to simply minimize transitions - an approach followed by previous research. Instead, Transition Pattern Coding (TPC) modifies the transition profile to minimize energy, and in many cases higher transition activity can result in lower energy. Results show that up to a factor of 2 reduction in energy.