Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power encodings for global communication in CMOS VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Introduction to data compression
Introduction to data compression
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis of low-overhead interfaces for power-efficient communication over wide buses
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power memory mapping through reducing address bus activity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Information-theoretic bounds on average signal transition activity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A spatially-adaptive bus interface for low-switching communication (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A$^{\mbox{\huge\bf 2}}$BC: adaptive address bus coding for low power deep sub-micron designs
Proceedings of the 38th annual Design Automation Conference
Low-energy for deep-submicron address buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Extension of the Working-Zone-Encoding Method to Reduce the Energy on the Microprocessor Data Bus
ICCD '98 Proceedings of the International Conference on Computer Design
An Adaptive Dictionary Encoding Scheme for SOC Data Buses
Proceedings of the conference on Design, automation and test in Europe
Some Issues in Gray Code Addressing
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power analysis of system-level on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Controlling inductive cross-talk and power in off-chip buses using CODECs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
DS2IS: Dictionary-based segmented inversion scheme for low power dynamic bus design
Journal of Systems Architecture: the EUROMICRO Journal
Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems
Transactions on High-Performance Embedded Architectures and Compilers I
Adaptive data compression for high-performance low-power on-chip networks
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
An efficient segmental bus-invert coding method for instruction memory data bus switching reduction
EURASIP Journal on Embedded Systems
Dynamic memory access management for high-performance DSP applications using high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus power estimation and power-efficient bus arbitration for system-on-a-chip embedded systems
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
| Hi-index | 0.00 |
As bus lengths on multihundred-million transistor systems-on-a-chip (SOC) grow, and as interwire capacitances of sub-0.10/µm technologies advance, the resulting high-switching capacitances of buses (and interconnects in general) have a nonnegligible impact on the power consumption of a whole SOC. This trend has been recognized and recently addressed by various research groups.We address this problem by introducing our bus encoding technique, adaptive dictionary-encoding scheme "ADES" that minimizes the power consumption of data buses through a dictionary-based encoding technique. Based on exploration of data properties on buses, our technique saves on average more than 25% of bus energy compared to the nonencoded cases using a large set of real-world applications for both address and data buses. Furthermore, we compare our technique to the best-known data bus encoding techniques to date and we find that it exceeds all of them in terms of energy savings for the same set of applications.