Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Search Procedure for Hamilton Paths and Circuits
Journal of the ACM (JACM)
Fast cache and bus power estimation for parameterized system-on-a-chip design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Address bus encoding techniques for system-level power optimization
Proceedings of the conference on Design, automation and test in Europe
Reducing Address Bus Transitions for Low Power Memory Mapping
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A dictionary-based en/decoding scheme for low-power data buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems
Transactions on High-Performance Embedded Architectures and Compilers I
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In a system-on-a-chip embedded system, an external bus connects embedded processor cores, I/O peripherals, direct memory access (DMA) and off-chip memory. The power on the external bus makes up a significant portion of the overall power use in the system. In this paper, we will focus on the address and control bus power on the external bus. We have developed an external bus power model which monitors memory bus state transitions and models power-efficient bus arbitration schemes power. Our model allows us to consider performance/power trade-offs in managing off-chip memory accesses. We use an Analog Devices ADSP-BF533 multimedia system-on-a-chip embedded system as our target architecture to validate our model. By using more power-efficient external bus arbitration schemes, we find we can reduce overall power by as much as 18%.