Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power encodings for global communication in CMOS VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Partial bus-invert coding for power optimization of system level bus
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Power optimization of core-based systems by address bus encoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Address bus encoding techniques for system-level power optimization
Proceedings of the conference on Design, automation and test in Europe
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Some Issues in Gray Code Addressing
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Architectures and synthesis algorithms for power-efficient bus interfaces
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Reducing transitions on memory buses using sector-based encoding technique
Proceedings of the 2002 international symposium on Low power electronics and design
Combining wire swapping and spacing for low-power deep-submicron buses
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A dictionary-based en/decoding scheme for low-power data buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Optimizing Array-Intensive Applications for On-Chip Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
BEAM: bus encoding based on instruction-set-aware memories
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Multi-parametric improvements for embedded systems using code-placement and address bus coding
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A variation-aware low-power coding methodology for tightly coupled buses
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Value-based bit ordering for energy optimization of on-chip global signal buses
Proceedings of the conference on Design, automation and test in Europe: Proceedings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Energy efficiency bounds of pulse-encoded buses
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Efficient RC low-power bus encoding methods for crosstalk reduction
Integration, the VLSI Journal
Control for power gating of wires
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Repeater insertion in power-managed VLSI systems
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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