Computer architecture and organization; (2nd ed.)
Computer architecture and organization; (2nd ed.)
Global instruction scheduling for superscalar machines
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Fast Prolog with an extended general purpose architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
SYCLOP: Synthesis of CMOS Logic for Low Power Applications
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Prolog Benchmark Suite for Aquarius
A Prolog Benchmark Suite for Aquarius
A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A multiple clocking scheme for low power RTL design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Cache design trade-offs for power and performance optimization: a case study
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Power analysis and low-power scheduling techniques for embedded DSP software
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Two dimensional codes for low power
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
System-level power optimization of special purpose applications: the beach solution
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Exploiting the locality of memory references to reduce the address bus energy
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Theoretical bounds for switching activity analysis in finite-state machines
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Power estimation for architectural exploration of HW/SW communication on system-level buses
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Selective instruction compression for memory energy reduction in embedded systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Power optimization of system-level address buses based on software profiling
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power minimization derived from architectural-usage of VLIW processors
Proceedings of the 37th Annual Design Automation Conference
Stability of long-lived consensus (extended abstract)
Proceedings of the nineteenth annual ACM symposium on Principles of distributed computing
Power-optimal encoding for DRAM address bus (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Address bus encoding techniques for system-level power optimization
Proceedings of the conference on Design, automation and test in Europe
Power optimization and management in embedded systems
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Low power techniques for address encoding and memory allocation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A$^{\mbox{\huge\bf 2}}$BC: adaptive address bus coding for low power deep sub-micron designs
Proceedings of the 38th annual Design Automation Conference
Low-energy for deep-submicron address buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Low power address encoding using self-organizing lists
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Software implementation strategies for power-conscious systems
Mobile Networks and Applications
Power-optimal encoding for a DRAM address bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Tuning of loop cache architectures to programs in embedded system design
Proceedings of the 15th international symposium on System Synthesis
Efficient power reduction techniques for time multiplexed address buses
Proceedings of the 15th international symposium on System Synthesis
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Application-driven processor design exploration for power-performance trade-off analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Coupling-aware high-level interconnect synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Synthesis of customized loop caches for core-based embedded systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Maximum power estimation for CMOS circuits using deterministic and statistic approaches
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Software-Only Bus Encoding Techniques for an Embedded System
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Memory Bus Encoding for Low Power: A Tutorial
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Maximum number of edges joining vertices on a cube
Information Processing Letters
Stability of long-lived consensus
Journal of Computer and System Sciences
Adaptive low-power address encoding techniques using self-organizing lists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
An evolutionary approach for reducing the energy in address buses
ISICT '03 Proceedings of the 1st international symposium on Information and communication technologies
Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Resource-constrained low-power bus encoding with crosstalk delay elimination
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power-Efficient Wakeup Tag Broadcast
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Partitioned bus coding for energy reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Loop scheduling with timing and switching-activity minimization for VLIW DSP
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of VLSI Signal Processing Systems
Adaptive and flexible dictionary code compression for embedded applications
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Algorithms and analysis of scheduling for loops with minimum switching
International Journal of Computational Science and Engineering
Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors
International Journal of High Performance Computing and Networking
Average Binary Long-Lived Consensus: Quantifying the Stabilizing Role Played by Memory
SIROCCO '08 Proceedings of the 15th international colloquium on Structural Information and Communication Complexity
Energy-efficient encoding techniques for off-chip data buses
ACM Transactions on Embedded Computing Systems (TECS)
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture
Journal of Signal Processing Systems
An efficient segmental bus-invert coding method for instruction memory data bus switching reduction
EURASIP Journal on Embedded Systems
Average long-lived binary consensus: Quantifying the stabilizing role played by memory
Theoretical Computer Science
Journal of Systems Architecture: the EUROMICRO Journal
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Maximum power estimation for CMOS circuits using deterministic and statistical approaches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The optimal strategy for the average long-lived consensus
CSR'11 Proceedings of the 6th international conference on Computer science: theory and applications
Energy-Aware system-on-chip for 5 GHz wireless LANs
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Average long-lived memoryless consensus: the three-value case
SIROCCO'10 Proceedings of the 17th international conference on Structural Information and Communication Complexity
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CMOS circuits consume power during the charging and discharging of capacitances. Reducing switching activity then, saves power in embedded processors. The authors' two-pronged attack uses Gray code addressing and cold scheduling to eliminate bit switches.