Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Code compression for embedded systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Pipeline gating: speculation control for energy reduction
Proceedings of the 25th annual international symposium on Computer architecture
Enhanced code compression for embedded RISC processors
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Code compression for low power embedded system design
Proceedings of the 37th Annual Design Automation Conference
Compiler techniques for code compaction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Low Power Digital CMOS Design
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
Compression of Embedded System Programs
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Control unit synthesis targeting low-power processors
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Code density optimization for embedded DSP processors using data compression techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Arithmetic Coding for Low Power Embedded System Design
DCC '00 Proceedings of the Conference on Data Compression
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Extensions to Programmable DSP architectures for Reduced Power Dissipation
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Some Issues in Gray Code Addressing
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Efficient execution of compressed programs
Efficient execution of compressed programs
Reducing code size with echo instructions
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
LZW-Based Code Compression for VLIW Embedded Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 3
IEEE Transactions on Computers
A decompression core for powerPC
IBM Journal of Research and Development
Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An Instruction Set Architecture Based Code Compression Scheme for Embedded Processors
DCC '05 Proceedings of the Data Compression Conference
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In embedded control applications, system cost and power/energy consumption are key considerations. In such applications, program memory forms a significant part of the chip area. Hence reducing code size reduces the system cost significantly. A significant part of the total power is consumed in fetching instructions from the program memory. Hence reducing instruction fetch power has been a key target for reducing power consumption. To reduce the cost and power consumption, embedded systems in these applications use application specific processors that are fine tuned to provide better solutions in terms of code density, and power consumption. Further fine tuning to suit each particular application in the targeted class can be achieved through reconfigurable architectures. In this paper, we propose a reconfiguration mechanism, called Instruction Re-map Table, to re-map the instructions to shorter length code words. Using this mechanism, frequently used set of instructions can be compressed. This reduces code size and hence the cost. Secondly, we use the same mechanism to target power reduction by encoding frequently used instruction sequences to Gray codes. Such encodings, along with instruction compression, reduce the instruction fetch power. We enhance Texas Instruments DSP core TMS320C27x to incorporate this mechanism and evaluate the improvements on code size and instruction fetch energy using real life embedded control application programs as benchmarks. Our scheme reduces the code size by over 10% and the energy consumed by over 40%.