A locally adaptive data compression scheme
Communications of the ACM
Data compression using dynamic Markov modelling
The Computer Journal
Text compression
Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Arithmetic coding for data compression
Communications of the ACM
Compression of Embedded System Programs
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Code density optimization for embedded DSP processors using data compression techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Trace-driven studies of VLIW video signal processors
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
Code compression based on operand factorization
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Selective instruction compression for memory energy reduction in embedded systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Evaluation of a high performance code compression method
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Procedure Based Program Compression
International Journal of Parallel Programming - Special issue on the 30th annual ACM/IEEE international symposium on microarchitecture, part II
Effective algorithms for cache-level compression
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Cached-code compression for energy minimization in embedded processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Cache-Memory Interfaces in Compressed Memory Systems
IEEE Transactions on Computers
Compressed Code Execution on DSP Architectures
Proceedings of the 12th international symposium on System synthesis
Generation of fast interpreters for Huffman compressed bytecode
Proceedings of the 2003 workshop on Interpreters, virtual machines and emulators
Survey of code-size reduction methods
ACM Computing Surveys (CSUR)
Variable Instruction Set Architecture and Its Compiler Support
IEEE Transactions on Computers
Compiler optimization and ordering effects on VLIW code compression
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
IEEE Transactions on Computers
High performance code compression architecture for the embedded ARM/THUMB processor
Proceedings of the 1st conference on Computing frontiers
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Proceedings of the international symposium on Code generation and optimization
Dynamic coalescing for 16-bit instructions
ACM Transactions on Embedded Computing Systems (TECS)
A compressed memory hierarchy using an indirect index cache
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
A dictionary construction technique for code compression systems with echo instructions
LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Profile-driven compression scheme for embedded systems
Proceedings of the 3rd conference on Computing frontiers
Journal of VLSI Signal Processing Systems
Adaptive and flexible dictionary code compression for embedded applications
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Adaptive object code compression
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Generation of fast interpreters for Huffman compressed bytecode
Science of Computer Programming - Special issue on advances in interpreters, virtual machines and emulators (IVME'03)
Effects of program compression
Journal of Systems Architecture: the EUROMICRO Journal
Code compression for performance enhancement of variable-length embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
Selective Code Compression Scheme for Embedded Systems
Transactions on High-Performance Embedded Architectures and Compilers I
Dictionary-based program compression on customizable processor architectures
Microprocessors & Microsystems
A universal placement technique of compressed instructions for efficient parallel decompression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cache aware compression for processor debug support
Proceedings of the Conference on Design, Automation and Test in Europe
Code compression for embedded VLIW processors using variable-to-fixed coding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An approach for code compression in run time for embedded systems: a preliminary results
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part I
A new technique for program code compression in embedded microprocessor
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
Microprocessors & Microsystems
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Memory is one of the most restricted resources in many modern embedded systems. Code compression can provide substantial savings in terms of size. In a compressed code CPU, a cache miss triggers the decompression of a main memory block, before it gets transferred to the cache. Because the code must be decompressible starting from any point (or at least at cache block boundaries), most file-oriented compression techniques cannot be used. We propose two algorithms to compress code in a space-efficient and simple to decompress way, one which is independent of the instruction set and another which depends on the instruction set. We perform experiments on two instruction sets, a typical RISC (MIPS) and a typical CISC (x86) and compare our results to existing file-oriented compression algorithms.