Instruction fetch mechanisms for VLIW architectures with compressed encodings
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Code compression for embedded systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Subword Parallelism with MAX-2
IEEE Micro
Architecture of a Broadband Mediaprocessor
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Datapath design for a VLIW Video Signal Processor
HPCA '97 Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture
Data-path synthesis of VLIW video signal processors
Proceedings of the 11th international symposium on System synthesis
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