Integer and combinatorial optimization
Integer and combinatorial optimization
On the Complexity of Scheduling Problems for Parallel/Pipelined Machines
IEEE Transactions on Computers
Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Scheduling time-critical instructions on RISC machines
ACM Transactions on Programming Languages and Systems (TOPLAS)
An Optimal Instruction Scheduler for Superscalar Processor
IEEE Transactions on Parallel and Distributed Systems
A recursive technique for computing lower-bound performance of schedules
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Code compression for embedded systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
A text-compression-based method for code size minimization in embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Lx: a technology platform for customizable VLIW embedded processing
Proceedings of the 27th annual international symposium on Computer architecture
Compiler techniques for code compaction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Optimal instruction scheduling using integer programming
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Re-configurable computing in wireless
Proceedings of the 38th annual Design Automation Conference
Hardware/software instruction set configurability for system-on-chip processors
Proceedings of the 38th annual Design Automation Conference
A fast approach to computing exact solutions to the resource-constrained scheduling problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design of an one-cycle decompression hardware for performance increase in embedded systems
Proceedings of the 39th annual Design Automation Conference
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Compression of Embedded System Programs
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
ICPP '97 Proceedings of the international Conference on Parallel Processing
Effective Compilation Support for Variable Instruction Set Architecture
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Evaluation of Search Heuristics for Embedded System Scheduling Problems
CP '01 Proceedings of the 7th International Conference on Principles and Practice of Constraint Programming
A Fast Algorithm for Scheduling Time-Constrained Instructions on Processors with ILP
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
Efficient Backtracking Instruction Schedulers
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
A decompression core for powerPC
IBM Journal of Research and Development
Compact and efficient code generation through program restructuring on limited memory embedded DSPs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 14.98 |
A variable instruction set processor provides a dictionary that enables the compiler to configure the best instruction set to use for executing the program being compiled. This paper describes Cognigine's variable instruction set communication architecture (VISC Architecture) and the implementation of a compiler that provides effective compilation and optimization support for this target. The compiler implementation involves the use of an abstract operation representation that enables the code generator to optimize toward the core architecture of the processor without committing to any specific instruction format. It then uses an enumeration approach to instruction scheduling that determines the final forms of the instructions to be generated while still adhering to the irregular constraints imposed by the architecture. The enumeration approach also allows the incorporation of dictionary reuse functionality to provide trade offs between program performance and dictionary budget. Finally, we provide experimental results to show the effectiveness of these compilation techniques in supporting Cognigine's VISC Architecture.