Integer and combinatorial optimization
Integer and combinatorial optimization
On the Complexity of Scheduling Problems for Parallel/Pipelined Machines
IEEE Transactions on Computers
A recursive technique for computing lower-bound performance of schedules
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Advanced compiler design and implementation
Advanced compiler design and implementation
Optimal instruction scheduling using integer programming
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
C Compiler Design for an Industrial Network Processor
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
A fast approach to computing exact solutions to the resource-constrained scheduling problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ICPP '97 Proceedings of the international Conference on Parallel Processing
Efficient Backtracking Instruction Schedulers
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
Adaptive explicitly parallel instruction computing
Adaptive explicitly parallel instruction computing
Some Experiments in Local Microcode Compaction for Horizontal Machines
IEEE Transactions on Computers
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Variable Instruction Set Architecture and Its Compiler Support
IEEE Transactions on Computers
VHC: Quickly Building an Optimizer for Complex Embedded Architectures
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Balancing register allocation across threads for a multithreaded network processor
Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation
Effective thread management on network processors with compiler analysis
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Compiler-Supported Thread Management for Multithreaded Network Processors
ACM Transactions on Embedded Computing Systems (TECS)
Data hiding in compiled program binaries for enhancing computer system performance
IH'05 Proceedings of the 7th international conference on Information Hiding
| Hi-index | 0.00 |
Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines the best instruction set to use for a given program and generates efficient code sequence based on it. We first give an overview of the VISC Architecture pioneered at Cognigine that exemplifies a Variable Instruction Set Architecture. We then present three compilation techniques that, when combined, enable us to provide effective compilation and optimization support for such an architecture. The first technique involves the use of an abstract operation representation that enables the code generator to optimize towards the core architecture of the processor without committing to any specific instruction format. The second technique uses an enumeration approach to scheduling that yields near-optimal instruction schedules while stilladhering to the irregular constraints imposed by the architecture. We then derive the dictionary and the instruction output based on this schedule. The third technique superimposes dictionary re-use on the enumeration algorithm to provide trade-off between program performance and dictionary budget. This enables us to make maximal use of the dictionary space without exceeding its limit. Finally, we provide measurements to show the effectiveness of these techniques.