Integer and combinatorial optimization
Integer and combinatorial optimization
On the Complexity of Scheduling Problems for Parallel/Pipelined Machines
IEEE Transactions on Computers
Scheduling time-critical instructions on RISC machines
ACM Transactions on Programming Languages and Systems (TOPLAS)
An Optimal Instruction Scheduler for Superscalar Processor
IEEE Transactions on Parallel and Distributed Systems
A recursive technique for computing lower-bound performance of schedules
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal instruction scheduling using integer programming
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
A fast approach to computing exact solutions to the resource-constrained scheduling problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ICPP '97 Proceedings of the international Conference on Parallel Processing
Effective Compilation Support for Variable Instruction Set Architecture
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Evaluation of Search Heuristics for Embedded System Scheduling Problems
CP '01 Proceedings of the 7th International Conference on Principles and Practice of Constraint Programming
A Fast Algorithm for Scheduling Time-Constrained Instructions on Processors with ILP
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
Efficient Backtracking Instruction Schedulers
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
Variable Instruction Set Architecture and Its Compiler Support
IEEE Transactions on Computers
Reducing code size in VLIW instruction scheduling
Journal of Embedded Computing - Low-power Embedded Systems
An Application of Constraint Programming to Superblock Instruction Scheduling
CP '08 Proceedings of the 14th international conference on Principles and Practice of Constraint Programming
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This paper describes the implementation of an instruction scheduler that produces near-optimal results by efficiently enumerating all possible schedules. The scheduler is implemented in the context of an embedded processor that allows compile-time configuration of the instruction set to use for each program, where the need to adhere to the tight and irregular hardware constraints were the original motivation for using this approach. We present techniques that speed up the enumeration process by coming up with good initial lower bound estimates for the schedules and by pruning off large areas of the search space through implicit enumeration. In the process, we found that taking the hardware constraints into account actually helps in speeding up the enumeration. We provide performance data that show that the enumeration approach is superior to heuristics-based approaches like list scheduling for our target processor. The data also show that the compile-time overhead associated with enumeration can be effectively contained. This justifies the deployment of enumeration-based instruction schedulers in commercial compilers targeting embedded processors with similar tight constraints.