Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
UET scheduling with unit interprocessor communication delays
Discrete Applied Mathematics
Computers and Operations Research
IBM RISC System/6000 processor architecture
IBM Journal of Research and Development
Instruction scheduling for the IBM RISC System/6000 processor
IBM Journal of Research and Development
i860 microprocessor architecture
i860 microprocessor architecture
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
IEEE Micro
Combinatorial Algorithms: Theory and Practice
Combinatorial Algorithms: Theory and Practice
A recursive time estimation algorithm for program traces under resource constraints
SAC '98 Proceedings of the 1998 ACM symposium on Applied Computing
Optimal instruction scheduling using integer programming
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
A Dynamic Programming Approach to Optimal Integrated Code Generation
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Optimal integrated code generation for clustered VLIW architectures
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Variable Instruction Set Architecture and Its Compiler Support
IEEE Transactions on Computers
Optimal Superblock Scheduling Using Enumeration
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Branch-and-bound task allocation with task clustering-based pruning
Journal of Parallel and Distributed Computing
Data-Dependency Graph Transformations for Instruction Scheduling
Journal of Scheduling
Data-Dependency Graph Transformations for Superblock Scheduling
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Reducing code size in VLIW instruction scheduling
Journal of Embedded Computing - Low-power Embedded Systems
Optimal trace scheduling using enumeration
ACM Transactions on Architecture and Code Optimization (TACO)
Constraint-Based register allocation and instruction scheduling
CP'12 Proceedings of the 18th international conference on Principles and Practice of Constraint Programming
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Performance in superscalar processing strongly depends on the compiler's ability to generate codes that can be executed by hardware in an optimal or near optimal order. Generating optimal code is an NP-complete problem. However, there is a need for highly optimized code, such as in superscalar or real-time systems. In this paper, an instruction scheduling scheme for optimizing a program trace is proposed. Optimized code can be arrived at without much redundant work, if some important features in code are well explored and utilized in scheduling. To formalize the task, two abstract models, one for a superscalar processor and the other for a program trace, are given. These two models reflect most of the characteristics of the scheduling problem. The interrelations between instructions and partial schedules are thoroughly studied, and dominance and equivalence relations on them are defined. These relations are then used to reduce the solution space and eventually help to produce optimal schedules. The results of experiments that show the promise of the proposed scheme are also presented.Index Terms驴Pipeline processors, sequencing and scheduling, optimization, prune and search, and NP-completeness.