Scheduling expressions on a pipelined processor with a maximal delay of one cycle
ACM Transactions on Programming Languages and Systems (TOPLAS)
The evolution of RISC technology at IBM
IBM Journal of Research and Development
Design of the IBM RISC System/6000 floating-point execution unit
IBM Journal of Research and Development
Instruction scheduling beyond basic blocks
IBM Journal of Research and Development
A compilation technique for software pipelining of loops with conditional jumps
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Local Microcode Compaction Techniques
ACM Computing Surveys (CSUR)
An overview of the PL.8 compiler
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Trace Scheduling: A Technique for Global Microcode Compaction
IEEE Transactions on Computers
The evolution of RISC technology at IBM
IBM Journal of Research and Development
Instruction scheduling beyond basic blocks
IBM Journal of Research and Development
Performance characteristics of architectural features of the IBM RISC System/6000
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
The Marion system for retargetable instruction scheduling
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Global instruction scheduling for superscalar machines
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Linear-time, optimal code scheduling for delayed-load architectures
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Comparing static and dynamic code scheduling for multiple-instruction-issue processors
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Efficient DAG construction and heuristic calculation for instruction scheduling
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Code duplication: an assist for global instruction scheduling
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Tolerating data access latency with register preloading
ICS '92 Proceedings of the 6th international conference on Supercomputing
Software support for speculative loads
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Performance evaluation of instruction scheduling on the IBM RISC System/6000
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Register allocation with instruction scheduling
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Balanced scheduling: instruction scheduling when memory latency is uncertain
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Scheduling time-critical instructions on RISC machines
ACM Transactions on Programming Languages and Systems (TOPLAS)
A novel framework of register allocation for software pipelining
POPL '93 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Enhanced superscalar hardware: the schedule table
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
SCISM: a scalable compound instruction set machine
IBM Journal of Research and Development
The POWER2 performance monitor
IBM Journal of Research and Development
Instruction scheduling in the TOBEY compiler
IBM Journal of Research and Development
An Optimal Instruction Scheduler for Superscalar Processor
IEEE Transactions on Parallel and Distributed Systems
Efficient instruction scheduling for delayed-load architectures
ACM Transactions on Programming Languages and Systems (TOPLAS)
Anticipatory instruction scheduling
Proceedings of the eighth annual ACM symposium on Parallel algorithms and architectures
Instruction scheduling for the Motorola 88110
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Resource usage models for instruction scheduling: two new models and a classification
ICS '99 Proceedings of the 13th international conference on Supercomputing
Scheduling time-constrained instructions on pipelined processors
ACM Transactions on Programming Languages and Systems (TOPLAS)
Backtracking-Based Instruction Scheduling to Fill Branch Delay Slots
International Journal of Parallel Programming
IEEE Transactions on Computers
ACM Transactions on Mathematical Software (TOMS)
IEEE Transactions on Computers
Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors
LCPC '99 Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing
Instruction Scheduling with Timing Constraints on a Single RISC Processor with 0/1 Latencies
CP '02 Proceedings of the 6th International Conference on Principles and Practice of Constraint Programming
Continuous program optimization: A case study
ACM Transactions on Programming Languages and Systems (TOPLAS)
Register allocation for optimal loop scheduling
CASCON '93 Proceedings of the 1993 conference of the Centre for Advanced Studies on Collaborative research: distributed computing - Volume 2
Efficient instruction scheduling for a pipelined architecture
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Balanced scheduling: instruction scheduling when memory latency is uncertain
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Contributions to the GNU compiler collection
IBM Systems Journal
Instruction Scheduling Across Control Flow
Scientific Programming
Learning heuristics for basic block instruction scheduling
Journal of Heuristics
The evolution of RISC technology at IBM
IBM Journal of Research and Development
Proof of correctness of high-performance 3-1 interlock collapsing ALUs
IBM Journal of Research and Development
Hi-index | 0.01 |