Branch folding in the CRISP microprocessor: reducing branch delay to zero
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Machine organization of the IBM RISC System/6000 processor
IBM Journal of Research and Development
Design of the IBM RISC System/6000 floating-point execution unit
IBM Journal of Research and Development
Instruction scheduling for the IBM RISC System/6000 processor
IBM Journal of Research and Development
Instruction scheduling beyond basic blocks
IBM Journal of Research and Development
Computation of elementary functions on the IBM RISC System/6000 processor
IBM Journal of Research and Development
An overview of the PL.8 compiler
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Optimization of range checking
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
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This paper traces the evolution of IBM RISC architecture from its origins in the 1970s at the IBM Thomas J. Watson Research Center to the present-day IBM RISC System/6000* computer. The acronym RISC, for Reduced Instruction-Set Computer, is used in this paper to describe the 801 and subsequent architectures. However, RISC in this context does not strictly imply a reduced number of instructions, but rather a set of primitives carefully chosen to exploit the fastest component of the storage hierarchy and provide instructions that can be generated easily by compilers. We describe how these goals were embodied in the 801 architecture and how they have since evolved on the basis of experience and new technologies. The effect of this evolution is illustrated with the results of several benchmark tests of CPU performance.