IBM RISC System/6000 processor architecture
IBM Journal of Research and Development
Design of the IBM RISC System/6000 floating-point execution unit
IBM Journal of Research and Development
Dhrystone: a synthetic systems programming benchmark
Communications of the ACM
Architecture of a VLSI instruction cache for a RISC
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
A study of branch prediction strategies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Design of a Computer—The Control Data 6600
Design of a Computer—The Control Data 6600
The evolution of RISC technology at IBM
IBM Journal of Research and Development
Design of the IBM RISC System/6000 floating-point execution unit
IBM Journal of Research and Development
Leading-zero anticipator (LZA) in the IBM RISC System/6000 floating-point execution unit
IBM Journal of Research and Development
The Evolution of Instruction Sequencing
Computer - Special issue on instruction sequencing
High-bandwidth data memory systems for superscalar processors
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Future general purpose supercomputer architectures
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Branch history table prediction of moving target branches due to subroutine returns
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Computer Architecture in the 1990s
Computer
Effects of building blocks on the performance of super-scalar architecture
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
A graphical comparison of RISC processors
ACM SIGARCH Computer Architecture News
Improving the accuracy of dynamic branch prediction using branch correlation
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Prefetching in supercomputer instruction caches
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Register connection: a new approach to adding registers into instruction set architectures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
POWER2 fixed-point, data cache, and storage control units
IBM Journal of Research and Development
POWER2 floating-point unit: architecture and implementation
IBM Journal of Research and Development
The POWER2 performance monitor
IBM Journal of Research and Development
Design considerations for the PowerPC 601 microprocessor
IBM Journal of Research and Development
Design at the system level with VLSI CMOS
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Architectural timing verification of CMOS RISC processors
IBM Journal of Research and Development - Special issue: IBM CMOS technology
A limit study of local memory requirements using value reuse profiles
Proceedings of the 28th annual international symposium on Microarchitecture
Hierarchical Execution to Speed Up Pipeline Interlock in Mainframe Computers
IEEE Transactions on Computers
The intrinsic bandwidth requirements of ordinary programs
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Trace cache: a low latency approach to high bandwidth instruction fetching
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Register renaming and dynamic speculation: an alternative approach
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors
IEEE Transactions on Parallel and Distributed Systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Proceedings of the 27th annual international symposium on Computer architecture
Testing for Function and Performance: Towards anIntegrated Processor Validation Methodology
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Optimizing a Superscalar Machine to Run Vector Code
IEEE Parallel & Distributed Technology: Systems & Technology
IEEE Micro
Developing the AMD-K5 Architecture
IEEE Micro
IEEE Micro
Reducing Branch Delay to Zero in Pipelined Processors
IEEE Transactions on Computers
Optimal 2-Bit Branch Predictors
IEEE Transactions on Computers
Algebraic Models of Superscalar Microprocessor Implementations: A Case Study
Proceedings of the ESPRIT Working Group 8533 on Prospects for Hardware Foundations: NADA - New Hardware Design Methods, Survey Chapters
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Adaptive Cache Compression for High-Performance Processors
Proceedings of the 31st annual international symposium on Computer architecture
I-cache multi-banking and vertical interleaving
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The evolution of RISC technology at IBM
IBM Journal of Research and Development
Partial address directory for cache access
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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