Optimizing a Superscalar Machine to Run Vector Code

Authors:
IEEE Parallel & Distributed Technology: Systems & Technology staff
Affiliations:
-
Venue:
IEEE Parallel & Distributed Technology: Systems & Technology
Year:
1993

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Abstract

A streamlined vector architecture and the IBM superscalar RISC System/6000 are discussed. It is shown, step-by-step, how each handles the same program. The factors that let vector machines outperform the RS/6000 are identified. Several extensions to the RS/6000 architecture that could help it attain vector-level performance on code with long vectors are proposed.