Instruction issue logic for high-performance, interruptable pipelined processors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Checkpoint repair for high-performance out-of-order execution machines
IEEE Transactions on Computers
Machine organization of the IBM RISC System/6000 processor
IBM Journal of Research and Development
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ACM SIGARCH Computer Architecture News
Implementation of precise interrupts in pipelined processors
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Advances in Computer Architecture
Advances in Computer Architecture
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Computer Architecture; A Quantitative Approach
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A semantics-based approach for the design and verification of concurrent processors
A semantics-based approach for the design and verification of concurrent processors
A look at several memory management units, TLB-refill mechanisms, and page table organizations
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Concurrent Event Handling through Multithreading
IEEE Transactions on Computers
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Proceedings of the 14th international conference on Supercomputing
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HiPC '01 Proceedings of the 8th International Conference on High Performance Computing
Energy-exposed instruction sets
Power aware computing
In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs)
IEEE Transactions on Computers
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This paper presents a taxonomy of interrupt processing strategies for concurrent processors. Such a taxonomy helps processor designers systematically explore possible interrupt processing system implementations. It also provides a framework to which new information about interrupt processing can easily be added. This paper also discusses other issues which relate to interrupt processing, such as preciseness, interrupt nesting, and interrupt- specific hardware.