MIPS RISC architecture
A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
Digital Technical Journal
Implementation of precise interrupts in pipelined processors
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Direct addressed caches for reduced power consumption
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Energy-Efficient Register Access
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
Compiling for vector-thread architectures
Proceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization
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Modern performance-oriented ISAs, such as RISC and VLIW, only expose to software features that impact the critical path through computation. Pipelined microprocessor implementations hide most of the microarchitectural work performed in executing instructions. Therefore, there is no incentive to expose these micro-operations, and their energy consumption is hidden from software.This work presents energy-exposed hardware-software interfaces to give software more fine-grain control over energy-consuming microarchitectural operations. We introduce software restart markers to make temporary processor state visible to software without complicating hardware exception management. This technique can enable a wide variety of energy optimizations. We implement exposed bypass latches which allow the compiler to eliminate register file traffic by directly targeting the processor bypass latches. Another technique, tagunchecked loads and stores, allows software to access cache data without a hard-ware tag check when the compiler can guarantee an access will be to the same line as an earlier access.