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This paper describes the precise exception model of the MC88110 symmetric superscalar microprocessor. The MC88110 is a superscalar, pipelined processor that contains multiple exection units and allows out-of order execution of instructions. The MC88110 implements fully precise exceptions and presents the architecturally correct state to an exception handling routine in a manner that minimizes exception response latency. The interrupt latency timings in the MC88110 are described, and several examples of short and long latencies are provided.