POWER2 fixed-point, data cache, and storage control units

Authors:
D. J. Shippy;T. W. Griffith
Affiliations:
-;-
Venue:
IBM Journal of Research and Development
Year:
1994

Citing 4
Cited 4

The IBM RISC System/6000 processor: hardware overview

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Machine organization of the IBM RISC System/6000 processor

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POWER2 floating-point unit: architecture and implementation

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The POWER2 performance monitor

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POWER2: next generation of the RISC System/6000 family

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POWER2 instruction cache unit

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The POWER2 performance monitor

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Exploiting functional parallelism of POWER2 to design high-performance numerical algorithms

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Abstract