POWER2: next generation of the RISC System/6000 family

POWER2 floating-point unit: architecture and implementation

IBM Journal of Research and Development

The POWER2 performance monitor

IBM Journal of Research and Development

Commercial workload performance in the IBM POWER2 RISC System/6000 processor

IBM Journal of Research and Development

Exploiting functional parallelism of POWER2 to design high-performance numerical algorithms

IBM Journal of Research and Development

Lattice QCD on the IBM scalable POWERParallel Systems SP2

Supercomputing '95 Proceedings of the 1995 ACM/IEEE conference on Supercomputing

The RISC processor DMN-6: a unified data-control flow architecture

ACM SIGARCH Computer Architecture News

Increasing memory bandwidth with wide buses: compiler, hardware and performance trade-offs

ICS '97 Proceedings of the 11th international conference on Supercomputing

Parallel processing of the shear-warp factorization with the binary-swap method on a distributed-memory multiprocessor system

PRS '97 Proceedings of the IEEE symposium on Parallel rendering

Efficient householder QR factorization for superscalar processors

ACM Transactions on Mathematical Software (TOMS)

Improving the memory-system performance of sparse-matrix vector multiplication

IBM Journal of Research and Development

Widening resources: a cost-effective technique for aggressive ILP architectures

MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture

Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures

IEEE Transactions on Computers

Measurement of a scientific workload using the IBM hardware performance monitor

SC '98 Proceedings of the 1998 ACM/IEEE conference on Supercomputing

Speculative dynamic vectorization

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture

Cluster assignment for high-performance embedded VLIW processors

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Exploiting Instruction- and Data-Level Parallelism

IEEE Micro

Modeling the Communication Performance of the IBM SP2

IPPS '96 Proceedings of the 10th International Parallel Processing Symposium

Exploration of the Performance of a Data Mining Application via Hardware Based Monitoring

The Journal of Supercomputing

Efficient parallel processing of competitive learning algorithms

Parallel Computing

High-performance and low-power VLIW cores for numerical computations

International Journal of High Performance Computing and Networking

POWER4 system microarchitecture

IBM Journal of Research and Development