Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Alpha architecture and first implementation
COMPCON '92 Proceedings of the thirty-seventh international conference on COMPCON
Performance of Various Computers Using Standard Linear Equations Software
Performance of Various Computers Using Standard Linear Equations Software
POWER2: next generation of the RISC System/6000 family
IBM Journal of Research and Development
The PowerPC 604 RISC microprocessor
IEEE Micro
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For part I, see ibid., vol.13, no.4, p.8-16 (1993). Two processors that compete in the workstation/server markets are compared. The 62.5-MHz IBM RISC System/6000 Model 580 exemplifies a moderate clock rate design. The 133-1200-MHz DEC Alpha processor represents an aggressive clock rate design. The performance implications of the memory subsystems and the effect of instruction sets on path length are described. It is shown that performance measurements on many systems support the initial claim that cycle time is not sufficient to determine performance.