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Complexity-effective superscalar processors
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Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Design of the PowerPC 604e microprocessor
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Register File Design Considerations in Dynamically Scheduled Processors
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A Statistically Rigorous Approach for Improving Simulation Methodology
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Complexity-Effective Reorder Buffer Designs for Superscalar Processors
IEEE Transactions on Computers
Isolating Short-Lived Operands for Energy Reduction
IEEE Transactions on Computers
A scalable, clustered SMT processor for digital signal processing
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
Instruction packing: reducing power and delay of the dynamic scheduling logic
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Improving Computer Architecture Simulation Methodology by Adding Statistical Rigor
IEEE Transactions on Computers
Power-Efficient Wakeup Tag Broadcast
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SATSim: a superscalar architecture trace simulator using interactive animation
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Scalable Dynamic Instruction Scheduler through Wake-Up Spatial Locality
IEEE Transactions on Computers
High performance set associative translation lookaside buffers for low power microprocessors
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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