Power-aware operand delivery

Authors:
Erika Gunadi;Mikko H. Lipasti
Affiliations:
University of Wisconsin;University of Wisconsin
Venue:
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Year:
2007

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Abstract

Based on operand delivery, existing microprocessors can be categorized into architected register file (ARF) or physical register file (PRF) machines, both with or without payload RAM (PL). Though many previous generation microprocessors use a PRF without PL, the trend of newer microprocessors targeting lower power environments seem to be moving towards ARF with PL. We quantitatively analyze power consumption of different machine styles: ARF with PL, ARF without PL, PRF with PL, and PRF only machine. Our result shows that PRF without PL consumes the least amount of power and is fundamentally the best approach for building power-aware out-of-order microprocessors.