A persistent rescheduled-page cache for low overhead object code compatibility in VLIW architectures
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Instruction fetch mechanisms for VLIW architectures with compressed encodings
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Performance characterization of a Quad Pentium Pro SMP using OLTP workloads
Proceedings of the 25th annual international symposium on Computer architecture
An out-of-order execution technique for runtime binary translators
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
MPS: Miss-Path Scheduling for Multiple-Issue Processors
IEEE Transactions on Computers
Dynamo: a transparent dynamic optimization system
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
OS and compiler considerations in the design of the IA-64 architecture
ACM SIGPLAN Notices
OS and compiler considerations in the design of the IA-64 architecture
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Bloom filtering cache misses for accurate data speculation and prefetching
ICS '02 Proceedings of the 16th international conference on Supercomputing
Direct load: dependence-linked dataflow resolution of load address and cache coordinate
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Implementation of the Exponential Function in a Floating-Point Unit
Journal of VLSI Signal Processing Systems
Itanium Processor Microarchitecture
IEEE Micro
Instruction-level parallel processors-dynamic and static scheduling tradeoffs
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
Address-free memory access based on program syntax correlation of loads and stores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Micro-operation cache: a power aware frontend for variable instruction length ISA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Evaluating the performance of dynamic branch prediction schemes with BPSim
WCAE-3 '97 Proceedings of the 1997 workshop on Computer architecture education
Effective support of simulation in computer architecture instruction
WCAE '02 Proceedings of the 2002 workshop on Computer architecture education: Held in conjunction with the 29th International Symposium on Computer Architecture
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
On the potential of latency tolerant execution in speculative multithreading
IFMT '08 Proceedings of the 1st international forum on Next-generation multicore/manycore technologies
Overview of complementary GaAs technology for high-speed VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leveraging Strength-Based Dynamic Information Flow Analysis to Enhance Data Value Prediction
ACM Transactions on Architecture and Code Optimization (TACO)
Disjoint out-of-order execution processor
ACM Transactions on Architecture and Code Optimization (TACO)
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
Tuning the continual flow pipeline architecture
Proceedings of the 27th international ACM conference on International conference on supercomputing
Virtual register renaming: energy efficient substrate for continual flow pipelines
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Tuning the continual flow pipeline architecture with virtual register renaming
ACM Transactions on Architecture and Code Optimization (TACO)
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This inside look at a large microprocessor development project reveals some of the reasoning (for goals, changes, trade-offs, and performance simulation) that lay behind its final form.