The floating point performance of a superscalar SPARC processor
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Predicting conditional branch directions from previous runs of a program
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Instruction-level parallel processing: history, overview, and perspective
The Journal of Supercomputing - Special issue on instruction-level parallelism
The multiflow trace scheduling compiler
The Journal of Supercomputing - Special issue on instruction-level parallelism
The Journal of Supercomputing - Special issue on instruction-level parallelism
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
Dynamic memory disambiguation using the memory conflict buffer
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Critical path reduction for scalar programs
Proceedings of the 28th annual international symposium on Microarchitecture
Software pipelining showdown: optimal vs. heuristic methods in a production compiler
PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation
Instruction scheduling for the HP PA-8000
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Region-based compilation: introduction, motivation, and initial experience
International Journal of Parallel Programming - Special issue on instruction-level parallel processing—part I
Tuning the Pentium Pro Microarchitecture
IEEE Micro
The MIPS R10000 Superscalar Microprocessor
IEEE Micro
Explicit multi-threading (XMT) bridging models for instruction parallelism (extended abstract)
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
| Hi-index | 4.10 |
Instruction-level parallelism allows a sequence of instructions derived from a sequential program to be parallelized for execution on multiple pipelined functional units. If industry acceptance is a measure of importance, ILP has blossomed. It now profoundly influences the design of almost all leading-edge microprocessors and their compilers. ILP's key advantage is that it exploits parallelism without requiring the programmer to rewrite existing applications. This is attractive because today's applications are still programmed sequentially, and many will never be rewritten. Exploiting ILP across a diverse set of performance-critical applications will require renewed emphasis on the role of the compiler. To advance, ILP compilers will require an enormous research effort, much like the one that drove vector compilers to today's relatively mature status. Thus far, however, ILP has yet to receive a similar investment, even though it presents what may be even more complex technical challenges. A number of ILP compilers exist both in academia and in industry, yet the development of ILP is far from complete.