Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Circular scheduling: a new technique to perform software pipelining
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
PA-RISC 2.0 architecture
Structure of Computers and Computations
Structure of Computers and Computations
Advanced performance features of the 64-bit PA-8000
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
MICRO 14 Proceedings of the 14th annual workshop on Microprogramming
Register-sensitive selection, duplication, and sequencing of instructions
ICS '01 Proceedings of the 15th international conference on Supercomputing
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The PA-8000 is capable of reordering independent operations at run time, a task normally performed only by the instruction scheduler in the compiler. This paper presents some of the unique issues faced by an instruction scheduler for the PA-8000. Several features of the micro-architecture are presented along with the heuristics used in the production compiler to model that feature. These features include latency, resource constraints, instruction polarity cache interfaces, and memory dependences. The performance results in the paper show that instruction scheduling remains an important compiler optimization, even for out of order machines.