A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
IMPACT: an architectural framework for multiple-instruction-issue processors
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Migrating a CISC computer family onto RISC via object code translation
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Sentinel scheduling for VLIW and superscalar processors
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
Data preload for superscalar and VLIW processors
Data preload for superscalar and VLIW processors
Dynamic rescheduling: a technique for object code compatibility in VLIW architectures
Proceedings of the 28th annual international symposium on Microarchitecture
PA-RISC 2.0 architecture
A persistent rescheduled-page cache for low overhead object code compatibility in VLIW architectures
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Fast, effective code generation in a just-in-time Java compiler
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
Tuning the Pentium Pro Microarchitecture
IEEE Micro
Shade: A Fast Instruction Set Simulator for Execution Profiling
Shade: A Fast Instruction Set Simulator for Execution Profiling
Machine-adaptable dynamic binary translation
DYNAMO '00 Proceedings of the ACM SIGPLAN workshop on Dynamic and adaptive compilation and optimization
Exploring the Interaction between Java's Implicitly Thrown Exceptions and Instruction Scheduling
International Journal of Parallel Programming
Instruction Scheduling in the Presence of Java's Runtime Exceptions
LCPC '99 Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing
Optimizing Java Programs in the Presence of Exceptions
ECOOP '00 Proceedings of the 14th European Conference on Object-Oriented Programming
Precise Exception Semantics in Dynamic Compilation
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Eliminating Exception Constraints of Java Programs for IA-64
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Hardware Support for Control Transfers in Code Caches
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Using Dynamic Binary Translation to Fuse Dependent Instructions
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Dynamic binary translation using run-time feedbacks
Science of Computer Programming - Software analysis, evolution and re-engineering
SuperPin: Parallelizing Dynamic Instrumentation for Real-Time Performance
Proceedings of the International Symposium on Code Generation and Optimization
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A dynamic translator emulates an instruction set architccturc by translating source instructions to native code during execution. On statically-scheduled hardware, higher performance can potentially be achieved by reordering the translated instructions; however, this is a challenging transformation if the source architecture supports precise exception semantics, and the user-level program is allowed to register exception handlers. This paper presents a software technique which allows a translator to achieve the out-of-order execution of user-level programs, while preserving all sequential semantics. The design combines a translator, an interpreter, and a set of operating system services. Using the proposed techniques, a dynamic translator can optimistically reorder instructions and speculate them across branch boundaries. If a mispeculated operation causes an exception, the recovery algorithm reverts the application state to a safe point, then retranslates the faulty code without reordering to disable further exceptions.