Two-level adaptive training branch prediction
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Tuning the Pentium Pro Microarchitecture
IEEE Micro
On the importance of points-to analysis and other memory disambiguation methods for C programs
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
Speculative precomputation: long-range prefetching of delinquent loads
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Post-pass binary adaptation for software-based speculative precomputation
PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
Using predicate path information in hardware to determine true dependences
ICS '02 Proceedings of the 16th international conference on Supercomputing
Real-time stereo within the VIDET Project
Real-Time Imaging
Peppermint and Sled: Tools for Evaluating SMP Systems Based on IA-64 (IPF) Processors
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
An EPIC Processor with Pending Functional Units
ISHPC '02 Proceedings of the 4th International Symposium on High Performance Computing
Reuse Distance-Based Cache Hint Selection
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
Journal of Symbolic Computation
Compiler managed micro-cache bypassing for high performance EPIC processors
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Predicate-aware scheduling: a technique for reducing resource constraints
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Phi-Predication for light-weight if-conversion
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Itanium 2 Processor Microarchitecture
IEEE Micro
Predicate prediction for efficient out-of-order execution
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Tiling, Block Data Layout, and Memory Hierarchy Performance
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the 1st conference on Computing frontiers
IEEE Transactions on Computers
Efficient formal verification of pipelined processors with instruction queues
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Using positive equality to prove liveness for pipelined microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Data Centric Cache Measurement on the Intel ltanium 2 Processor
Proceedings of the 2004 ACM/IEEE conference on Supercomputing
A PC-based real-time stereo vision system
Machine Graphics & Vision International Journal
An accurate cost model for guiding data locality transformations
ACM Transactions on Programming Languages and Systems (TOPLAS)
Constructing Virtual Architectures on a Tiled Processor
Proceedings of the International Symposium on Code Generation and Optimization
Predicate gates for spatial logic
ICCOMP'07 Proceedings of the 11th WSEAS International Conference on Computers
High performance set associative translation lookaside buffers for low power microprocessors
Integration, the VLSI Journal
Online Estimation of Architectural Vulnerability Factor for Soft Errors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Finding representative workloads for computer system design
Finding representative workloads for computer system design
A method for debugging of pipelined processors in formal verification by correspondence checking
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessors
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Automatic formal verification of reconfigurable DSPs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Bridge floating-point fused multiply-add design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
RIMP: runtime implicit predication
APPT'05 Proceedings of the 6th international conference on Advanced Parallel Processing Technologies
Dual-stack return address predictor
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
Evaluating performance of BLAST on intel xeon and itanium2 processors
ISPA'04 Proceedings of the Second international conference on Parallel and Distributed Processing and Applications
Automatic formal verification of multithreaded pipelined microprocessors
Proceedings of the International Conference on Computer-Aided Design
Automatic formal verification of liveness for pipelined processors with multicycle functional units
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Discerning the dominant out-of-order performance advantage: is it speculation or dynamism?
Proceedings of the eighteenth international conference on Architectural support for programming languages and operating systems
LUCAS: latency-adaptive unified cluster assignment and instruction scheduling
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Support for dynamic issue width in VLIW processors using generic binaries
Proceedings of the Conference on Design, Automation and Test in Europe
Speculative hardware/software co-designed floating-point multiply-add fusion
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
CAeSaR: unified cluster-assignment scheduling and communication reuse for clustered VLIW processors
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
| Hi-index | 0.00 |
This article describes the microarchitecture of the Itanium(tm) processor, which is the first implementation of the IA-64 instruction set architecture. The processor is optimized to meet a wide range of requirements - high performance on Internet servers and workstations, support for 64bits of addressing, reliability for mission-critical applications, full IA-32 instruction set compatibility in hardware, and scalability across a range of operating systems and platforms