Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Verification of a simple pipelined machine model
Computer-Aided reasoning
ACM Transactions on Computational Logic (TOCL)
Proceedings of the 38th annual Design Automation Conference
Computer Architecture: Complexity and Correctness
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Boolean satisfiability with transitivity constraints
ACM Transactions on Computational Logic (TOCL)
Computer architecture: a quantitative approach
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Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
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Information and Computation
Itanium Processor Microarchitecture
IEEE Micro
Relating Multi-step and Single-Step Microprocessor Correctness Statements
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Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Herbrand Automata for Hardware Verification
CONCUR '98 Proceedings of the 9th International Conference on Concurrency Theory
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CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Elementary Microarchitecture Algebra
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Formal Verification of VLIW Microprocessors with Speculative Execution
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Liveness with (0, 1, infty)-Counter Abstraction
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Journal of Symbolic Computation
Experience with Term Level Modeling and Verification of the M*Core microprocessor Core.
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Formal Verification of an Avionics Microprocessor
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Algebraic specification and verification of processor microarchitectures
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Proceedings of the conference on Design, automation and test in Europe - Volume 1
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient reduction of finite state model checking to reachability analysis
International Journal on Software Tools for Technology Transfer (STTT)
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using positive equality to prove liveness for pipelined microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Comparative Study of Strategies for Formal Verification of High-Level Processors
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Proving the Correctness of Multiprocess Programs
IEEE Transactions on Software Engineering
Formal Verification of Pipelined Microprocessors with Delayed Branches
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A method for debugging of pipelined processors in formal verification by correspondence checking
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Automatic formal verification of reconfigurable DSPs
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Optimization techniques for verification of out-of-order execution machines
Journal of Electrical and Computer Engineering
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
Automatic formal verification of multithreaded pipelined microprocessors
Proceedings of the International Conference on Computer-Aided Design
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Presented is a highly automatic approach for proving bounded liveness of pipelined processors with multicycle functional units, without the need for the user to set up an inductive argument. Multicycle functional units are abstracted with a placeholder that is suitable for proving both safety and liveness. Abstracting the branch targets and directions with arbitrary terms and formulas, respectively, that are associated with each instruction, made the branch targets and directions independent of the data operands. The observation that the term variables abstracting branch targets of newly fetched instructions can be considered to be in the same equivalence class, allowed the use of a dedicated fresh term variable for all such branch targets and the abstraction of the Instruction Memory with a generator of arbitrary values. To further improve the scaling, the multicycle ALU was abstracted with a placeholder without feedback loops. Also, the equality comparison between the terms written to the PC and the dedicated fresh term variable for branch targets of new instructions was implemented as part of the circuit, thus avoiding the need to apply the abstraction function along the specification side of the commutative diagram for liveness. This approach resulted in 4 orders of magnitude speedup for a 5-stage pipelined DLX processor with a 32-cycle ALU, compared to a previous method for indirect proof of bounded liveness, and scaled for a 5-stage pipelined DLX with a 2048-cycle ALU.