ACM Transactions on Computational Logic (TOCL)
Proceedings of the 38th annual Design Automation Conference
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Journal of Symbolic Computation
Formal Verification of a Complex Pipelined Processor
Formal Methods in System Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Modeling and validation of pipeline specifications
ACM Transactions on Embedded Computing Systems (TECS)
Efficient formal verification of pipelined processors with instruction queues
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using positive equality to prove liveness for pipelined microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Parallelization Scheme Based on Work Stealing for a Class of SAT Solvers
Journal of Automated Reasoning
Comparison of schemes for encoding unobservability in translation to SAT
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A method for debugging of pipelined processors in formal verification by correspondence checking
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessors
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Automatic formal verification of reconfigurable DSPs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
Automatic formal verification of multithreaded pipelined microprocessors
Proceedings of the International Conference on Computer-Aided Design
Automatic formal verification of liveness for pipelined processors with multicycle functional units
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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