MIPS RISC architectures
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
SPARC architecture, assembly language programming, and C
SPARC architecture, assembly language programming, and C
Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ACM Transactions on Computational Logic (TOCL)
Computer Architecture: Complexity and Correctness
Computer Architecture: Complexity and Correctness
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Relating Multi-step and Single-Step Microprocessor Correctness Statements
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Experience with Term Level Modeling and Verification of the M*Core microprocessor Core.
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Formal Verification of a Complex Pipelined Processor
Formal Methods in System Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using positive equality to prove liveness for pipelined microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Challenges in the Formal Verification of Complete State-of-the-Art Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Automatic formal verification of liveness for pipelined processors with multicycle functional units
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Integrating formal verification into an advanced computer architecture course
IEEE Transactions on Education
Automated formal verification of processors based on architectural models
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
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Presented is an approach for formal verification of pipelined microprocessors with delayed branches, i.e., branch instructions whose immediately following instruction is always executed regardless of whether the branch is taken. Delayed branches are used in the instruction sets of the MIPS, SPARC, and PA-RISC architectures. Because of their sequential semantics that spans several consecutive instruction slots, delayed branches complicate the checking of safety and liveness for pipelined designs. The presented approach is highly automatic compared to previous methods for formal verification of pipelined processors with delayed branches.