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ACM Computing Surveys (CSUR)
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DAC '96 Proceedings of the 33rd annual Design Automation Conference
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IEEE Transactions on Computers
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Mechanically Checking a Lemma Used in an Automatic Verification Tool
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
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FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
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CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation
CSD '98 Proceedings of the 1998 International Conference on Application of Concurrency to System Design
Hardware Modeling Using Function Encapsulation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Using Randomization and Learning to Solve Hard Real-World Instances of Satisfiability
CP '02 Proceedings of the 6th International Conference on Principles and Practice of Constraint Programming
CP '02 Proceedings of the 8th International Conference on Principles and Practice of Constraint Programming
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Challenges in the Formal Verification of Complete State-of-the-Art Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A method for debugging of pipelined processors in formal verification by correspondence checking
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessors
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Automatic formal verification of reconfigurable DSPs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
Automatic formal verification of multithreaded pipelined microprocessors
Proceedings of the International Conference on Computer-Aided Design
The algebra of equality proofs
RTA'05 Proceedings of the 16th international conference on Term Rewriting and Applications
Automatic formal verification of liveness for pipelined processors with multicycle functional units
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Desynchronization: design for verification
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
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We present a collection of ideas that allows the pipeline verification method pioneered by Burch and Dill [5] to scale very efficiently to dual-issue superscalar processors. We achieve a significant speedup in the verification of such processors, compared to the result by Burch [6], while using an entirely automatic tool. Instrumental to our success are exploiting the properties of positive equality [3][4] and the simplification capabilities of BDDs.