Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation

Authors:
Miroslav N. Velev;Randal E. Bryant
Affiliations:
-;-
Venue:
CSD '98 Proceedings of the 1998 International Conference on Application of Concurrency to System Design
Year:
1998

Citing 0
Cited 4

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Equivalence checking for behaviorally synthesized pipelines

Proceedings of the 49th Annual Design Automation Conference

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Abstract

This paper makes the idea of memory shadowing [5] applicable to symbolic ternary simulation. Memory shadowing, an extension of Burch and Dill's pipeline verification method [6] to the bit level, is a technique for providing on-the-fly identical initial memory state to two different memory execution sequences. We also present an algorithm which compares the final states of two memories for ternary correspondence, as well as an approach for generating efficiently the initial state of memories. These techniques allow us to verify that a pipelined circuit has behavior corresponding to that of its unpipelined specification by simulating two symbolic ternary execution sequences and comparing their final memory states. Experimental results show the potential of the new ideas.